september 2012 ? 2008 fairchild semiconductor corporation www.fairchildsemi.com 74AUP1G96 ? rev. 1.0.1 74AUP1G96 ? tinylogic ? low power universal configurable two- input logic gate (o pen drain output) 74AUP1G96 tinylogic ? low power universal configurable two-input logic gate (open drain output) features ? 0.8 v to 3.6v v cc supply operation ? 3.6 v over-voltage tolerant i/os at v cc from 0.8 v to 3.6 v ? extremely high speed t pd - 3.2 ns: typical at 3.3 v ? power-off high-impedance inputs and outputs ? low static power consumption - i cc =0.9 a maximum ? low dynamic power consumption - c pd =3.0 pf typical at 3.3 v ? ultra-small micropak? packages description the 74AUP1G96 is a universal configurable. two-input logic gate with an open-drain output that provides a high-performance and low-power solution for battery- powered portable applications. this product is designed for a wide low voltage operating range (0.8 v to 3.6 v) and guarantees very low static and dynamic power consumption across the entire voltage range. all inputs are implemented with hysteresis to allow for slower transition input signals and better switching noise immunity. the 74AUP1G96 provides for multiple functions as determined by various configurat ions of the three inputs. the potential logic functions provided are mux, and, or, nand, and, nor inverter and buffer ( see figure 2 to figure 8 ). ordering information part number top mark package packing method 74AUP1G96l6x ap 6-lead, micropa k? 1.0 x 1.45mm, jedec mo-252 5000 units on tape & reel 74AUP1G96fhx ap 6-lead, micropak2?, 1x1mm body, .35mm pitch 5000 units on tape & reel
? 2008 fairchild semiconductor corporation www.fairchildsemi.com 74AUP1G96 ? rev 1.0.1 2 74AUP1G96 ? tinylogic ? low power universal configurable two- input logic gate (o pen drain output) pin configurations figure 1. micropak? (top through view) pin definitions pin # name description 1 b data input 2 gnd ground 3 a data input 4 y output (open drain) 5 v cc supply voltage 6 c data input function table inputs y=output c b a l l l h (1) l l h h (1) l h l l l h h l h l l h (1) h l h l h h l h (1) h h h l h = high logic level l = low logic level note: 1. high impedance output state, open drain. 2-input logic function connection configuration 2-to-1 mux with inverted output figure 2 2-input nand gate figure 3 2-input nor gate with o ne inverted input figure 4 2-input and gate with one inverted input figure 4 2-input nand gate with one inverted input figure 5 2-input or gate with one inverted input figure 5 2-input nor gate figure 6 buffer figure 7 inverter figure 8 1 b 2 gnd 3 6 5 4 a c v cc y
? 2008 fairchild semiconductor corporation www.fairchildsemi.com 74AUP1G96 ? rev 1.0.1 3 74AUP1G96 ? tinylogic ? low power universal configurable two- input logic gate (o pen drain output) logic configurations figure 2 through figure 8 show the logical functions that can be implemented us ing the 74aup1g98. the diagrams show the demorgan?s equivalent logic duals for a given two-input function. the logical implementation is next to the board-level physical implementation of how the pins of the function should be connected. note: 2. when c is l, y=b. 3. when c is h, y=a. figure 2. 2-to-1 mux with inverted output figure 3. 2-input nand gate figure 4. input nor gate with one inverted input 2-input and gate with one inverted input figure 5. 2-input nand gate with one inverted input 2-input or gate with one inverted input figure 6. 2-input nor gate figure 7. buffer figure 8. inverter 1 2 3 6 5 4 b y c v cc b a c y a gnd 1 2 3 6 5 4 a y c v cc c y a gnd 1 2 3 6 5 4 a y c v cc c y a c y a gnd c y b c y b 1 2 3 6 5 4 b y c v cc gnd 1 2 3 6 5 4 b y c v cc c y b gnd 1 2 3 6 5 4 y c v cc y c gnd 1 2 3 6 5 4 y v cc y b gnd b
? 2008 fairchild semiconductor corporation www.fairchildsemi.com 74AUP1G96 ? rev. 1.0.1 4 74AUP1G96 ? tinylogic ? low power universal configurable two- input logic gate (o pen drain output) absolute maximum ratings stresses exceeding the absolute maximum ratings may dam age the device. the device may not function or be operable above the recommended operating conditions and stressi ng the parts to these levels is not recommended. in addition, extended exposure to stresses above the recomm ended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter min. max. unit v cc supply voltage -0.5 4.6 v v in dc input voltage -0.5 4.6 v v out (2) dc output voltage -0.5 4.6 v i ik dc input diode current v in < 0 v -50 ma i ok dc output diode current v out < 0 v -50 ma i ol dc output sink current +50 ma i cc or i gnd dc v cc or ground current per supply pin 50 ma t stg storage temperature range -65 +150 c t j junction temperature under bias +150 c t l junction lead temperature, soldering 10s +260 c p d power dissipation at +85c micropak-6? 130 mw micropak2?-6 120 esd human body model, jedec:jesd22-a114 4000 v charged device model, jedec:jesd22-c101 2000 note: 2. i o absolute maximum rating must be observed. recommended operating conditions (3) the recommended operating conditions table defines the conditions for actual device operation. recommended operating conditions are specified to ens ure optimal performance to the datasheet specificatio ns. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter condition min. max. unit v cc supply voltage 0.8 3.6 v v in input voltage 0 3.6 v v out output voltage 0 3.6 v i ol output current v cc =3.0 v to 3.6 v 4.0 ma v cc =2.3 v to 2.7 v 3.1 v cc =1.65 v to 1.95 v 1.9 v cc =1.4 v to 1.6 v 1.7 v cc =1.1 v to 1.3 v 1.1 v cc =0.8 v 20.0 a t a operating temperature, free air -40 +85 c ja thermal resistance micropak-6? 500 c/w micropak2?-6 560 note: 3. unused inputs must be held high or low. they may not float.
? 2008 fairchild semiconductor corporation www.fairchildsemi.com 74AUP1G96 ? rev. 1.0.1 5 74AUP1G96 ? tinylogic ? low power universal configurable two- input logic gate (o pen drain output) dc electrical characteristics symbol parameter v cc condition t a =25c t a =-40 to 85c unit min. max. min. max. v p positive threshold voltage 0.80 0.30 0.60 0.30 0.60 v 1.10 0.53 0.90 0.53 0.90 1.40 0.74 1.11 0.74 1.11 1.65 0.91 1.29 0.91 1.29 2.30 1.37 1.77 1.37 1.77 3.00 1.88 2.29 1.88 2.29 v n negative threshold voltage 0.80 0.10 0.60 0.10 0.60 v 1.10 0.26 0.65 0.26 0.65 1.40 0.39 0.75 0.39 0.75 1.65 0.47 0.84 0.47 0.84 2.30 0.69 1.04 0.69 1.04 3.00 0.88 1.24 0.88 1.24 v h hysteresis voltage 0.80 0.07 0.50 0.07 0.50 v 1.10 0.08 0.46 0.08 0.46 1.40 0.18 0.56 0.18 0.56 1.65 0.27 0.66 0.27 0.66 2.30 0.53 0.92 0.53 0.92 3.00 0.79 1.31 0.79 1.31 v ol low level output voltage 0.80 v cc 3.60 i ol =20 a 0.10 0.10 v 1.10 v cc 1.30 i ol =1.1 ma 0.30 x v cc 0.30 x v cc 1.40 v cc 1.60 i ol =1.7 ma 0.31 0.37 1.65 v cc 1.95 i ol =1.9 ma 0.31 0.35 2.30 v cc 2.70 i ol =3.1 ma 0.44 0.45 2.70 v cc 3.60 i ol =4.0 ma 0.44 0.45 i in input leakage current 0 v to 3.6 v 0 v in 3.6 v 0.1 0.5 a i off power off leakage current 0 v 0 (v in , v o ) 3.6 v 0.2 0.6 a i off additional power off leakage current 0 v to 0.2 v v in or v o =0 v to 3.6 v 0.2 0.6 a i cc quiescent supply current 0.8 v to 3.6 v v in - v cc or gnd 0.5 0.9 a v cc v in 3.6 v 0.9 i cc increase in i cc per input 3.3 v v in =v cc -0.6 v 40.0 50.0 a
? 2008 fairchild semiconductor corporation www.fairchildsemi.com 74AUP1G96 ? rev. 1.0.1 6 74AUP1G96 ? tinylogic ? low power universal configurable two- input logic gate (o pen drain output) ac electrical characteristics symbol parameter v cc condition t a =25c t a =-40 to 85c unit min. typ. max. min. max. t pzl , t plz propagation delay 0.80 c l =15 pf, r u =r d =5 k v i = 2 x (v cc ) ( see figure 9 ) 30 1.10 v cc 1.30 1.0 10.1 18.9 1.0 19.9 1.40 v cc 1.60 1.0 6.6 11.4 1.0 12.2 1.65 v cc 1.95 1.0 6.3 8.7 1.0 9.7 2.30 v cc 2.70 1.0 4.7 6.9 1.0 7.5 3.00 v cc 3.60 1.0 4.6 6.8 1.0 7.4 c in input capacitance 0 0.8 pf c out output capacitance 0 1.7 pf c pd power dissipation capacitance 0.80 v in =0 v or v cc , f=10 mhz 3.0 pf 1.10 v cc 1.30 3.1 1.40 v cc 1.60 3.2 1.65 v cc 1.95 3.4 2.30 v cc 2.70 3.8 3.00 v cc 3.60 4.4
? 2008 fairchild semiconductor corporation www.fairchildsemi.com 74AUP1G96 ? rev. 1.0.1 7 74AUP1G96 ? tinylogic ? low power universal configurable two- input logic gate (o pen drain output) ac loadings and waveforms notes: 4. c l includes load and stray capacitance. 5. input prr = 1.0 mhz, t w = 500 ns. figure 9. ac test circuit figure 10. a c waveforms symbol v cc 3.3 v 0.3 v 2.5 v 0.2 v 1.8v 0.15 v 1.5 v 0.10 v 1.2 v 0.10 v 0.8 v v mi v cc /2 v cc /2 v cc /2 v cc /2 v cc /2 v cc /2 v mo v ol + 0.3v v ol + 0.15v v ol + 0.15v v ol + 0.1v v ol + 0.1v v ol + 0.1v
? 2008 fairchild semiconductor corporation www.fairchildsemi.com 74AUP1G96 ? rev. 1.0.1 8 74AUP1G96 ? tinylogic ? low power universal configurable two- input logic gate (o pen drain output) physical dimensions figure 11. 6-lead, micropak?, 1.0 mm wide package drawings are provided as a service to customers consi dering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packagi ng area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . tape and reel specifications please visit fairchild semiconductor?s online packaging area for the most re cent tape and reel specifications: http://www.fairchildsemi.com/products/logic/pdf/micropak_tr.pdf . package designator tape section cavity number cavity status cover type status l6x leader (start end) 125 (typical) empty sealed carrier 5000 filled sealed trailer (hub end) 75 (typical) empty sealed 2. dimensions are in millimeters 1. conforms to jedec standard m0-252 variation uaad 4. filename and revision: mac06arev4 notes: 3. drawing conforms to asme y14.5m-1994 top view recommened land pattern bottom view 1.45 1.00 a b 0.05 c 0.05 c 2x 2x 0.55max 0.05 c (0.49) (1) (0.75) (0.52) (0.30) 6x 1x 6x pin 1 detail a 0.075 x 45 chamfer 0.25 0.15 0.35 0.25 0.40 0.30 0.5 (0.05) 1.0 5x detail a pin 1 terminal 0.40 0.30 0.45 0.35 0.10 0.00 0.10 cba 0.05 c c 0.05 c 0.05 0.00 5x 5x 6x (0.13) 4x 6x pin 1 identifier (0.254) 5. pin one identifier is 2x length of any 5 other line in the mark code layout.
? 2008 fairchild semiconductor corporation www.fairchildsemi.com 74AUP1G96 ? rev. 1.0.1 9 74AUP1G96 ? tinylogic ? low power universal configurable two- input logic gate (o pen drain output) physical dimensions figure 12. 6-lead, micropak2?, 1x1 mm body, .35 mm pitch package drawings are provided as a service to customers consi dering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packagi ng area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ . tape and reel specifications please visit fairchild semiconductor?s online packaging area for the most re cent tape and reel specifications: http://www.fairchildsemi.com/packaging/micropak2_6l_tr.pdf . package designator tape section cavity number cavity status cover type status fhx leader (start end) 125 (typical) empty sealed carrier 5000 filled sealed trailer (hub end) 75 (typical) empty sealed 1.00 b. dimensions are in millimeters. c. dimensions and tolerances per asme y14.5m, 1994 notes: a. complies to jedec mo-252 standard 0.05 c a b 0.55max 0.05 c c 0.35 0.09 0.19 123 0.35 0.25 5x 6x detail a 0.60 (0.08) 4x (0.05) 6x 0.40 0.30 0.075x45 chamfer 5x 0.40 0.35 1x 0.45 6x 0.19 top view bottom view 0.66 0.10 cba .05 c 0.89 pin 1 0.05 c 2x 2x 1.00 d. landpattern recommendation is based on fsc e. drawing filename and revision: mgf06arev3 0.52 0.73 0.57 0.20 6x 1x 5x recommended land pattern for space constrained pcb detail a pin 1 lead scale: 2x alternative land pattern for universal application design. 0.90 min 250um 65 4 0.35 (0.08) 4x side view
? 2008 fairchild semiconductor corporation www.fairchildsemi.com 74AUP1G96 ? rev. 1.0.1 10 74AUP1G96 ? tinylogic ? low power universal configurable two- input logic gate (o pen drain output)
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